Industrial control networks are one example of data communication systems wherein network nodes are attached to multiple communication networks to provide redundant communication between the network nodes.
As an example, the so-called Parallel Redundancy Protocol (PRP) is a data communication network standardized by the International Electrotechnical Commission as IEC 62439-3 Clause 4. PRP allows systems to overcome any single network failure without affecting the data transmission. Each network node of a PRP network has two Ethernet ports attached to two different local area networks (LANs). Each frame is substantially duplicated and sent substantially concurrently by a transmitting node over the two LANs. The PRP network may hereby provide redundant transmission over the two LANs. A receiving node can thus receive each frame via each of the two LANs and can process the frame that arrives first and discard the other. Herein, the receiving node may use the sequence number that is attached to each frame, and incremented for successive frames. PRP was developed to overcome any single network failure and to provide a high-availability network. In PRP, the duplicate frames as transmitted are identical apart from one or more bits of a so-called Redundancy Control Trailer (RCT) that comprises the sequence number of the frame, a network identifier and a frame size parameter. A frame may further be supplemented with a so-called Field Check Sequence (FCS) to provide a cyclic redundancy check. Destination address, source address, a so-called payload field comprising the data to be transmitted (hereafter referred to as information), sequence number and frame size parameter are identical between duplicate frames, whereas the network identifier and, if present, the FCS are different. As the frames are near to identical, such frames may further be referred to as plesio-identical frames. Similar protocols use parallel redundancy but comprise more non-identical fields, for example, not only differing by a limited number of bits in a trailer, but also differing by further control or status bits in a header. Such frames may further be referred to as quasi-identical.
For low baud rate communication, also UART-based field busses are used with networks with redundant communication. For example, the so-called Profibus (Process Field Bus) is a standard for field bus communication widely used in industrial process control and automation. In an exemplary Profibus communication system, an RS-485 UART is used as its physical layer. Herein, frame-oriented serial transmission over two different serial networks is used. In many Profibus systems, the frames transmitted over the different networks may be exactly identical.
Identical, plesio-identical and quasi-identical frames may further be referred to as redundant frames or as duplicate frames.
Transmission of duplicate frames may further be referred to as duplicast. Duplicast may be used in industrial control and automation as indicated above, as well as in, for example, automotive control systems, streaming audio or video, and other systems requiring reliable, non-interrupted communication. Other real-time systems may make a larger number of copies and concurrently transmit three or more copies via a corresponding number of different networks, Transmission of two, three or more copies via a corresponding number of different networks may further be referred to as multicast. Where the term duplicast is used in examples to described transmission over two networks, the skilled person will appreciate that the example may be extended to multicast transmission over more than two networks.
An exemplary prior art communications processor having a duplicast transmitter is schematically illustrated in FIG. 1a. FIG. 1a shows a communications processor UCP1 comprising a central processing unit (CPU) CPUP1 and a duplicast transmitter MPTDEVP1 for transmitting redundant data using a PRP protocol. The duplicast transmitter MPTDEVP1 comprises a processor RISCEP1, a local memory LOCMEMP1 comprising a first local buffer WA_MAC1 and a second local buffer WA_MAC2, a first transmitter EMAC1 and a second transmitter EMAC2 comprising respective transmitter buffers TxFIFO_MAC1 and TxFIFO_MAC2 and respective transmitter ports TPORTP1 and TPORTP2, and—in a variant of the prior art example—a hardware synchronization unit SYNCHW1. The transmitter ports TPORTP1 and TPORTP2 are connected to two different LANs LAN_1 and LAN_2. The transmitters EMAC1 and EMAC2 are arranged to transmit data buffered in the transmitter buffers TxFIFO_MAC1 and TxFIFO_MAC2 via the transmitter ports TPORTP1 and TPORTP2. The local memory LOCMEMP1 may also be referred to as work area. The first local buffer WAMAC1, the second local buffer WA_MAC2 and the transmitter buffers TxFIFO_MAC1, TxFIFO_MAC2 are implemented as cyclic First-In-First-Out (FIFO) buffers in local random access memory (RAM). In this example, the processor RISCEP1 is a reduced instruction set computing (RISC) processor.
The central processing unit CPUP1 and the duplicast transmitter MPTDEVP1 are connected to an external memory EXTMEMP1. The external memory EXTMEMP may be a DDR memory. The external memory EXTMEMP is used to store the data to be transmitted via each of the transmitters in two data buffers DBUF_MAC1 and DBUF_MAC2 in the external memory EXTMEMP.
The redundant transmission by the prior art communications processor UCP1 may be schematically illustrated with reference to numbers 1-8 shown in circles in FIG. 1a. 
Based on the address and length of a frame stored in PRP format in the external memory at a position in the first data buffer DBUF_MAC1 in the external memory EXTMEMP1, the CPU CPUP1 generates a first descriptor DESCR_MAC1 pointing to the frame and stores the first descriptor in a first transmission queue TQP1 in external memory EXTMEMP1 in a first action 1. The descriptor DESCR_MAC1 may for example be in a format as schematically illustrated in FIG. 1b: the descriptor DESCR_MAC1 may comprise a status and control field DSTATCTRL, a data length DLEN indicating the length of the frame and a data address DPNT providing a pointer to a start address of the frame in the external memory. The status and control field DSTATCTRL may comprise a so-called buffer ready flag, indicating whether data is available at the respective position. Next, in a second action 2, the CPU CPUP1 copies the frame from the first data buffer DBUF_MAC1 in the external memory to a second data buffer DBUF_MAC2 in the external memory. If required, the CPU CPUP1 changes the content of the frame for the second transmitter in between reading the frame from the first data buffer DBUF_MAC1 and writing the frame to the second data buffer DBUF_MAC2. For example this changing may comprise modifying the content of the frame by modifying the network identifier in the RCT. Subsequently, in a third action 3, generates the corresponding descriptor DESCR_MAC2 and stores the second descriptor in a second transmission queue TQP2. Thus, after action 3, plesio-identical copies of the frame are available in the first and second data buffer DBUF_MAC1, DBUF_MAC2 in the external memory EXTMEMP1. In a next action 4, the processor RISCEP1 reads the first descriptor DESCR_MAC1 from the first transmission queue TQP1 and decodes the first descriptor DESCR_MAC1 to obtain the length and the start address of the frame stored in the first data buffer DBUF_MAC1, reads the frame either entirely or in parts at a time from the first data buffer DBUF_MAC1 in dependence on the first descriptor DESCR_MAC1 via a direct memory access (DMA), and writes the frame or the parts of the frame at appropriate sizes and positions in a first local FIFO WA_MAC1. Hereby, the frame or the parts of the frame are read as one or more data blocks of data stored in external memory EXTMEMP1, and written into the first local FIFO WA_MAC1. In an exemplary prior art example, action 4 comprises a first DMA read to read the descriptor DESCR_MAC1 as stored in the transmission queue TQP1 from the external memory EXTMEMP and a subsequent DMA read or subsequent DMA reads to read the frame MAC1 as stored in the first data buffer DBUF_MAC1 from the external memory EXTMEMP. In a next action 5, the processor RISCEP1 reads the second descriptor DESCR_MAC2 from the second transmission queue TQP2, decodes the second descriptor DESCR_MAC2 to obtain the length and the start address of the frame stored in second data buffer DBUF_MAC2, and reads the frame either entirely or in parts at a time from the second data buffer DBUF_MAC2 in dependence on the second descriptor DESCR_MAC2 via DMA and writes the frame in data blocks of appropriate sizes at positions in a second local FIFO WA_MAC2. In some prior art example, the size of a DMA access in action 4 corresponds to the block size used to store the frame in the first data buffer in action 4 and the size of a DMA access in action 5 corresponds to the block size used to store the frame in the second data buffer in action 5. In other prior art examples, the size of a DMA accesses and block size for storing in the first and second local buffers DBUF_MAC1, DBUF_MAC2 may be different; for example, the size of a DMA access may be larger than the block size in the local FIFO, in which case the data read in one DMA access is written into multiple blocks in the first and second data buffer DBUF_MAC1, DBUF_MAC2 respectively. Then, in action 6, the processor RISCEP1 checks whether the first transmitter buffer TxFIFO_MAC1 has free space to store one or more data blocks, and as long as there is free space, reads a data block from a respective position in the first local buffer WA_MAC1, processes the data block in a first thread, and writes the data block as processed into the first transmitter buffer TxFIFO_MAC1 of the first transmitter MAC1. Next, in action 7, the processor RISCEP1 checks whether the second transmitter buffer TxFIFO_MAC2 has free space to store one or more data blocks, and as long as there is free space, reads a data block from a respective positions in the second local buffer WA_MAC2, processes the data block in a second thread —separate from the first thread but executing substantially the same processing on the data block read from the second local buffer as the processing performed by first thread on the data block read from the first local buffer—and writes the data block as processed into the second transmitter buffer TxFIFO_MAC2 of the second transmitter MAC2. Typically, the first and second transmitters EMAC1, EMAC2 are arranged to inform the processor RISCEP1 that there is space in their respective first or second transmitter buffer TxFIFO_MAC1, TxFIFO_MAC2 by providing a request to the processor RISCEP1 to write data into their respective first or second transmitter buffers. The checking whether the first or second transmitter buffer thus typically comprises checking whether such requests are pending from the respective first or second transmitter EMAC1, EMAC2.
In prior art duplicast transmitter MPTDEVP1 without a hardware synchronization unit SYNCHW1, the first and second transmitters EMAC1, EMAC2 transmit the data buffered in the respective transmitter buffers as soon as the data has arrived. This may result in indeterminate transmission of the two plesio-identical frames as action 8, because of, for example, a significant and possibly variable latency due to copying the duplicate frames and the (second) descriptor in the external memory and reading the descriptors and the duplicate frames from the external memory and the RISC RISCEP1 temporally processing each request using one thread for EMAC1 and another thread for EMAC2 or using the same thread for EMAC1 and EMAC2. To prevent this, prior art duplicast transmitter MPTDEVP1 typically comprise additional components, in particular a hardware synchronization unit SYNCHW1 as shown in FIG. 1a to synchronize the transmission by the first and second transmitters EMAC1, EMAC2 to hereby obtain a synchronized transmission of the two plesio-identical frames as action 8. The hardware synchronization unit SYNCHW1 hereto waits for a first data block of a frame to be written to the first transmitter buffer TxFIFO_MAC1 of the first transmitter EMAC1 from the first local FIFO WAMAC1. The hardware synchronization unit SYNCHW1 then waits for a first data block of a plesio-identical frame to be written to the second transmitter buffer TxFIFO_MAC2 of the second transmitter EMAC2 from the second local FIFO WA_MAC2. The hardware synchronization unit SYNCHW1 then triggers synchronous transmission of both blocks on transmitter ports TPORTP1 and TPORTP2. This synchronous transmission uses hardware acceleration in hardware synchronization unit SYNCHW1 to monitor blocks and configure over which ports the hardware synchronization unit SYNCHW1 hardware operates and typically usage of the same clock source for transmitter ports TPORTP1 and TPORTP2. This can be inherently difficult in duplicast schemes and be inherently difficult to scale for multicast schemes. In addition the act of waiting for both first blocks or in some instances the frame to be written to the first and second local FIFOs WAMAC1 and WA_MAC2 increases the transmission latency for at least one of the frames in a duplicast scheme.
FIG. 2 shows another prior art example. FIG. 2 shows a communications processor UCP2 comprising a central processing unit (CPU) CPUP2 and a duplicast transmitter MPTDEVP2 for transmitting redundant data using a PRP protocol. The duplicast transmitter MPTDEVP2 comprises, similar to the duplicast transmitter MPTDEVP1 shown in FIG. 1a, a processor RISCEP2, a local memory LOCMEMP1 comprising a first local buffer WA_MAC1 and a second local buffer WA_MAC2, a first transmitter EMAC1 and a second transmitter EMAC2 comprising respective transmitter buffers TxFIFO_MAC1 and TxFIFO_MAC2 and respective transmitter ports TPORTP1 and TPORTP2, and—in a variant of the prior art example—a hardware synchronization unit SYNCHW1. The CPU CPUP2 and the duplicast transmitter MPTDEVP2 are connected to an external memory EXTMEMP2. The external memory EXTMEMP2 is used to store the data to be transmitted via each of the transmitters in a single data buffer DBUF_MAC12 in the external memory EXTMEMP2. Components and actions that are substantially the same as in the duplicast transmitter MPTDEVP1 shown in FIG. 1a, reference is made to the description above.
The duplicast transmitter MPTDEVP2 shown in FIG. 2 differs from that in FIG. 1a, in particular that action 2, copying the frame stored in external memory to another location in external memory, is omitted as the frames transmitted on both transmitters are identical, and that in action 3, the CPU CPUP2 generates descriptors DESCR_MAC2 for the second transmission queue TQP2 which have pointers referring to the same locations in external memory as the corresponding descriptors DESCR_MAC1 of the first transmission queue TQP2. Actions 1, 3, 4, 5, 6, 7 and 8 are further substantially the same as described with reference to FIG. 1a. In FIG. 1a and FIG. 2 the software on CPUP1 and CPUP2 has to maintain and manage a plurality of transmit queues for a corresponding plurality of transmitters, even if the frames are identical in FIG. 1a and FIG. 2 or plesio-identical in FIG. 1a. 
As with the example shown in FIG. 1a, indeterminate transmission of the two plesio-identical frames may arise. The transmission of the two frames may, for example, show a significant and possibly variable latency, which may arise from copying the (second) descriptor in the external memory, reading the descriptors from the external memory, reading the frames from the external memory in action 4 and 5 without hardware synchronization unit SYNCHW1 and the RISC RISCEP2 temporally processing each request using one thread for EMAC1 and another thread for EMAC2 or using the same thread. Some prior art systems therefore use a hardware synchronization unit SYNCHW1 to synchronize the transmission by the first and second transmitters EMAC1, EMAC2, as in FIG. 1a, this comes at the cost of additional circuitry and does not reduce the latency arising from accessing the external memory via multiple DMA accesses to the multiple data buffers (such as the first and second data buffers DBUF_MAC1 and DBUF_MAC2) in external memory EXTMEMP.
FIG. 3 shows a prior art example wherein the transmitters comprising serial transmitters UMAC1, UMAC2, arranged to transmit data over two parallel serial networks SER_1, SER2. The serial transmitters may be arranged to use e.g. ProfiBUS or another RS-485 Universal Asynchronous receiver/transmitter (UART)-based serial protocol. Serial networks may be used, for example, in applications with a relatively low data rate.
The example shown in FIG. 3 shows a communications processor UCSP1 comprising a central processing unit (CPU) CPUS1 and a duplicast transmitter MPTDEVUP1 for transmitting redundant data using a RS-485 serial protocol. The duplicast transmitter MPTDEVUP1 comprises a processor RISCUP1, a plurality of arrays of registers comprising a first array of registers GPR_1 and a second array of registers GPR_2, a first transmitter UMAC1 and a second transmitter UMAC2 comprising respective transmitter buffers UTxFIFO_MAC1 and UTxFIFO_MAC2 and respective transmitter ports UPORTP1 and UPORTP2, and—in a variant of the prior art example—a hardware synchronization unit USYNC1. The transmitter ports UPORTP1 and UPORTP2 are connected to two different serial networks SER_1 and SER_2. The transmitters UMAC1 and UMAC2 are arranged to transmit data buffered in the transmitter buffers UTxFIFO_MAC1 and UTxFIFO_MAC2 via the transmitter ports UPORTP1 and UPORTP2. The plurality of arrays of registers may also be referred to as work area. The first array of registers GPR_1 and the second array of registers GPR_2 may also be referred to as local buffers. The transmitter buffers UTxFIFO_MAC1, UTxFIFO_MAC2 are implemented as cyclic First-In-First-Out (FIFO) buffers in local random access memory (RAM). In this example, the processor RISCUP1 is a reduced instruction set computing (RISC) processor.
The central processing unit CPUS1 and the duplicast transmitter MPTDEVUP1 are connected to an external memory EXTMEMUP. The external memory EXTMEMUP may be a DDR memory. The external memory EXTMEMUP is used to store the data to be transmitted via each of the transmitters in two data buffers DBUF_MAC1U and DBUF_MAC2U in the external memory EXTMEMUP. The duplicast transmitter MPTDEVUP1 is thus arranged to transmit data stored in the two data buffers DBUF_MAC1U and DBUF_MAC2U in external memory EXTMEMUP via the first and second transmitter buffers UTxFIFO_MAC1, UTxFIFO_MAC2 and the transmitter ports UPORTP1, UPORTP2.
The architecture of the example shown in FIG. 3 is largely similar to the architecture of the prior art example shown in FIG. 1a. For subsystems, components and actions that are substantially similar or substantially the same as described with FIG. 1a, reference is therefore made to the description above.
Because of the relatively low data rate used for serial transmission, there is no need to use a FIFO to store the frames or blocks read from the external memory EXTMEMUP. Accordingly, the example shown in FIG. 3 differs from the prior art Ethernet example shown in FIG. 1a in that the local buffer does not comprise two FIFOs WAMAC1, WAMAC2 capable to store one or more frames and/or data blocks, but the two arrays of registers GPR_1, GPR_2. Consequently, in action 4, the processor RISCUP1 reads the first descriptor DESCR_MAC1U from first transmission queue TQP1U, decodes the first descriptor DESCR_MAC1U to obtain the length and the start address of the frame stored in the first data buffer DBUF_MAC1U, reads the frame either entirely or one data block at a time from the first data buffer DBUF_MAC1U in dependence on the first descriptor DESCR_MAC1U via a direct memory access (DMA), and stores the frame in data blocks of appropriate sizes at positions in the first array of registers GPR_1, and, in action 5, the processor RISCUP1 reads the second descriptor DESCR_MAC2U from second transmission queue TQP2U, decodes the second descriptor DESCR_MAC2U to obtain the length and the start address of the frame stored in the second data buffer DBUF_MAC2U, reads the frame from the second data buffer DBUF_MAC2U in dependence on the second descriptor DESCR_MAC2U via DMA, and stores the frame in data blocks of appropriate sizes at positions in the second array of registers GPR_2. Then, in action 6, the processor RISCUP1 checks whether the first transmitter buffer UTxFIFO_MAC1 has free space to store one or more data blocks, and as long as there is free space, reads a data block from the first array of registers GPR_1, processes the data block in a first thread, and writes the data block as processed into the first transmitter buffer UTxFIFO_MAC1 of the first transmitter UMAC1. Next, in action 7, the processor RISCUP1 checks whether the second transmitter buffer UTxFIFO_MAC2 has free space to store one or more data blocks, reads a data block from the second array of registers GPR_2, processes the data block in a second thread —separate from the first thread but executing substantially the same processing on the data block read from the second array of registers as the processing performed by first thread on the data block read from the first array of registers—and writes the data block as processed into the second transmitter buffer UTxFIFO_MAC2 of the second transmitter UMAC2. Typically, the first and second transmitters UMAC1, UMAC2 are arranged to inform the processor RISCUP1 that there is space in their respective first or second transmitter buffer UTxFIFO_MAC1, UTxFIFO_MAC2 by providing a request to the processor RISCUP1 to write data into their respective first or second transmitter buffers. The checking whether the first or second transmitter buffer thus typically comprises checking whether such requests are pending from the respective first or second transmitter UMAC1, UMAC2. The other actions 1-3, and 8 may be similar as described with reference to FIG. 1a, with the arrays of registers substantially taking the places of the FIFOs WA_MAC1, WA_MAC2.
In variants of the prior art examples described above, the order of some of the actions may be different. For example in FIG. 3, after action 4 wherein the frame is read from the first data buffer DBUF_MAC1U and written to the first array of registers GPR_1, action 6 could be executed and result in transmission, before action 5 is executed. This may further increase latency and jitter observed.
For similar reasons as described with reference to FIG. 1a for an Ethernet-based multi-port transmitter, indeterminate transmission of the two plesio-identical frames may arise for the UART-based multi-port transmitter described with reference to FIG. 3.